Improved performance in integrated circuits requires technology scaling. As technology is scaled, the physical dimensions of transistors, such as gate oxide thickness and transistor gate length, are reduced. The operating voltage of the transistor must scale to maintain an acceptable electric field across the gate oxide to maintain acceptable reliability. Lowering the operating voltage requires that the threshold voltage of the transistor be reduced. Transistor off-state leakage current consists of sub-threshold leakage, gate direct tunnel current, and band-to-band tunnel leakage current. The relationship of transistor off-state leakage currents with respect to device scaling is shown by Inukai, et al., in “Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration”, IEEE Custom Integrated Circuit Conference, 19-2-1, 2000.
Inukai et al. teach that the sub-threshold leakage of the transistor becomes increasing large from one technology node to the next technology. At the same time, the gate leakage current of the transistor also increases as a result of reduction in gate oxide thickness. It has been reported that the gate leakage current increases by an order of magnitude for each 2 Angstrom reduction in gate oxide thickness. (Hamzaoglu et al., “Circuit-Level Techniques to Control Gate Leakage for sub-100 nm CMOS”, ISLPED. p. 60-63, August 2002.) Inukai et al. project that the gate leakage current will exceed the sub-threshold leakage current and become the dominating factor in leakage at some technology node. Therefore, standby power becomes more and more problematic in technology scaling.
Circuit techniques to suppress leakage currents have been proposed in the literature. Kuroda et al. propose a VTMOS technique to suppress standby leakage current in “0.9V. 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme”, IEEE Journal of Solid-State Circuits, vol. 31. pp. 1770-1779, 1996. In this VTMOS technique, the transistor is back-biased to raise the threshold voltage of the transistor in a standby mode. This technique can reduce the transistor sub-threshold leakage current, but does not reduce the gate tunneling leakage current.
Mutoh et al. propose an MTMOS technique in “I-V Power Supply High-Speed Digital Circuit Technology With Multi-Threshold Voltage CMOS”, IEEE Journal of Solid-State Circuit, vol. 30, pp. 847-854, 1995. This MTMOS technique uses a transistor having a high threshold voltage (Vt) to supply a virtual VDD supply voltage and a ground supply voltage to core circuitry. The high Vt transistor has the same gate oxide thickness as transistors in the core circuitry, but is less leaky. However, the MTMOS technique faces a similar problem as the VTMOS technique. That is, the MTMOS technique does not reduce gate leakage current.
Inukai et al. propose a BGMOS technique. The BGMOS technique uses a thicker oxide transistor as a power switch to shut-off the leakage path in a standby mode. However, the disadvantage of this technique is that the stored data are lost in standby mode. Inukai et al. propose adding a memory cell to store the data in standby mode. However, this proposed solution results in a significant increase in area penalty.
It would therefore be desirable to have a technique that can reduce both the gate tunneling leakage and sub-threshold leakage while maintaining the circuit state without significantly increasing the area penalty for the upcoming technology node.
Note that programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), have a significantly higher static power consumption than dedicated logic devices, such as standard-cell application specific integrated circuits (ASICs). A reason for this high static power consumption is that for any given design, a PLD only uses a subset of the available resources. The unused resources are necessary for providing greater mapping flexibility to the PLD. However, these unused resources still consume static power in the form of leakage current. Consequently, PLDs are generally not used in applications where low static power is required.
It would therefore be desirable to reduce the static power consumption of integrated circuits such as PLDs.